This invention is generally related to testing integrated circuits and, more particularly, to a method for testing imbedded repetitive structures, such as register arrays, wherein a test pattern generation algorithm takes advantage of the regularity of the structure without significantly modifying the test pattern generation software or the manufacturing test tools.
With the increasing density and size of Application Specific Integrated Circuits (ASICs) there has been an increasing tendency toward repetitive instantiation of logic structures. In some cases, these are referred to bit-slices, wherein a multi-bit data structure is built from several copies of a single bit data structure. Other cases include instantiation of multiple input and output macros, multiple processor cores, or two-dimensional arrays of switching elements to form, e.g., a cross-point switch.
Current test structures, methodologies, and Automated Test Pattern Generation (ATPG) software do not take advantage of structural regularity, resulting in larger test data volumes and longer test times. Essentially, the logic in an ASIC is treated as flat, random logic. A typical example of a regular structure consists of Register Arrays (RA). As the name suggests, they are highly regular structures having the array and read multiplexing treated as independent but identical bit-slices. Since ASICs typically have a large number of register arrays, often with more storage elements in the arrays than that found in conventional (random) logic, and since such arrays are inherently more difficult to test due to the addressing requirements, the problem of testing such ASICs has become unmanageable.
Today""s ASICs typically include one or more of five basic types of storage. These are: single bit registers, latches and Shift Register Latches (SRLs) used in random logic; Register Arrays (RAs) consisting of an array of registers or latches with appropriate addressing and clocking logic; Static Random Access Memory (SRAM) arrays, Dynamic Random Access Memory (DRAM) arrays; and, finally, Read Only Memories (ROM). The latter three are specialized circuits and are tested by specific deterministic patterns applied either by a tester or by so-called Built-In-Self-Test (BIST) logic built within the chip. The first two are commonly tested by test patterns generated uniquely for each such ASIC by ATPG software. For a xe2x80x9cfull scanxe2x80x9d ASIC, all the storage elements of the first two types are modified to support both the normal function and a special test scan mode. These scannable storage elements are then connected together to form scan chains accessible by the tester.
In addition to storage arrays, it has become increasingly common to find functional blocks in the chip replicated several times. As a result, many chips have significant portions of their logic organized as repeated structures. Current ATPG techniques are unable to take advantage of this repetition, leading to an excessive test data volume and test application times.
While individual storage elements of the RA are scannable and, therefore, controllable and observable for test purposes, they are surrounded by address decoding logic that makes the application of test patterns tedious. In order to sensitize a fault within the array, many of the bits of address and control information must be set to specific values. Due to the mutually exclusive decoding of addresses, it prevents the test generator from simultaneously testing any other faults in the array unless they happen to fall within the same, already addressed, word. Even then, unless all the control conditions for the two candidate faults are identical it is still impossible to test both faults with a single pattern.
Current ATPG software randomly selects a single fault from a list of untested faults throughout the entire chip and generates a test pattern to test that fault. The test pattern is then fault simulated, and any faults detected (presumably including the target fault) are identified as tested. This is repeated until no additional testable faults remain. The regularity of any repeated structure in the ASIC, such as the bit slices of register arrays, is completely ignored. By taking advantage of the repetitive structures, a test pattern generated for a fault in a single instance of the repeated structures could be used to detect the same fault in all other instances. To achieve this, all storage elements in each instance of the repetitive structure must be loaded with the same test stimuli.
The number of patterns required to test the RAs has become a significant problem as the number of scannable elements (SRLs) in the RAs within a typical ASIC significantly exceeds the number of SRLs in the rest of the logic. This has led to long scan chains, increasing the test application time and high test pattern count, all of which increases the test data volume. The test time and volumes of the largest ASICs being built often overwhelm current testers.
FIG. 1A shows a typical Register Array (RA) (1) to be tested by conventional methodology. Logically, the RA is a two dimensional array of scannable latches to which selecting means (2) are added on the base of a multi-bit signal called Write Address, wherein a subset of the latches modifies their content by way of multi-bit data stored in an external Write Data Register (6). Further, there is also provided a second selecting means (3) based on a multi-bit signal called Read Address, wherein a subset of these latches are used for observing multi-bit signals called Read Data. The two dimensional array is logically organized along one dimension into single dimension arrays called Word (4), each having the same length, and along the second dimension into single dimension arrays called Bit Slice (5), again each of the same length. Word (4) is a subset of the array selected by the Write and Read Address decoding logic (2 and 3), wherein the latches in the word are ordered. A bit slice (5) includes a single latch or bit from each word (4), the latch having the same ordinal position within each of the words.
For testing purposes, all the latches in the array are scannable and are organized into one or more scan chain segments. An additional scan chain segment may exist for the Write Data Register (6). One or more scan chains (one is shown herein) are connected to the start of some scan chain segments (7). Further, one or more the segments may be connected serially (9) before the scan chains are routed to other scannable elements within the design (8).
To generate test patterns, a fault is selected somewhere within the chip. A plurality of stimulus bits, referred to as a test cube, are generated to test the fault and observe the results. Test cubes are merged as long as there is no conflict between the bits required for each test cube. Once a sufficient number of cubes is merged, the remaining bits of the scan data to be scanned into the scan chains are filled, usually with random data, to create a test pattern. The test pattern is then simulated to determine what faults have been detected, and those faults are removed from the list of untested faults.
Still referring to FIG. 1A, to test a fault in one of the Register Array storage elements (10) which can be identified as existing at the intersection of word (4) and bit slice (5), specific values for the Write Address register, Read Address register, and storage element (10) to be tested, a bit in the Write Data (6) and Read Data registers must be specified as part of the test cube, and those values scanned into the correct positions in the overall scan chains.
Although the array is a regularly repeated structure, even in the case when the scan chain segments within the array are designed to conform to a bit-slice (as shown), the serial connections of the scan chain segments take no advantage of these facts. Every bit of the scan chain is totally independent of every other bit. Yet, the corresponding fault of a different latch of the same word (4) requires that the same Read Address and Write Address values, and the same data be scanned into the additional latch in the word, and, possibly, into another bit of the Write Data (6) and Read Data Registers. Clearly, these two patterns can be merged since most of the data are identical. In fact, if the data to be scanned into a latch in Register Array (10) is scanned into all the latches of the targeted word (4), and if the same write data is scanned into all the bits of the Write Data Register (6), then the same fault will be tested at every latch of the selected word, not just one, with little more information than the original test cube. The odds of its happening in normal test generation is low, partly because the test generator is specifically designed for unstructured logic, and as such, attempts to select faults that are scattered around the chip rather than in logical proximity in order to improve merging of test cubes. Thus, in traditional scan testing of a Register Array, the organization of scan chain segments in the Register Array is unimportant, and the regularity of the array is ignored.
Attempts have been made in the past to resolve these problems in two ways: 1) by overriding the write address decoding so that more than one word at a time is selected, increasing the odds of testing more than one fault in an RA with a single pattern, and 2) by modifying the ATPG software to recognize equivalency groups of faults in each word that the ATPG targets, and to target all faults in an equivalence group jointly rather than singularly. This last approach has not gained wide acceptance since, in many cases, it provides little reduction in test data volume (duplicate stimulus data must be fed over several scan streams) and no improvement in test with pseudo-random patterns as in Logic BIST.
Current ATPG programs are unable to take into consideration multiple, repeated, structures because of the inherent assumption built into all ATPG programs, and all Design For Test rules, that data in different memory elements of the scan chains should be independent of all each other. That is, the data should be uncorrelated. When testing random logic, i.e., wherein an arbitrary subset of the storage elements in the scan chains feed an arbitrary Boolean expression, this independence is required to avoid non-testable faults. Indeed, within a single repeated structure, this requirement for independence of the stimulus data still holds. However, when a structure is repeated multiple times, and each copy of the structure is independent of other copies, then, identical (fully correlated) stimulus data may be scanned into each copy of the structure without creating non-testable faults.
Accordingly, it is an object of the present invention to test imbedded repetitive structures in integrated circuit chips and modules.
It is a further object to test the imbedded repetitive structures by having the test generation software take advantage of the regularity of the structure without introducing significant changes to the test pattern generation software or to the manufacturing test tools.
It is yet another object to substantially reduce the number of patterns, the pattern data volume, and the length of the scan chains used for testing the imbedded repetitive structures.
It is a more particular object to test the imbedded repetitive structures by structuring and connecting the scan chain segments of the repeated structures in a way that forces identical test stimuli to be loaded into each copy of the repeated structure.
It is a further object to provide means for compressing the test results that can be observed during scan by the tester to show any fault that was observed.
In a first aspect of the invention, there is provided a digital logic chip or module under test consisting of multiple instantiations of identical and separately identifiable structures built of some mix of combinational logic and sequential elements, the sequential elements being commonly referred to as registers, latches, flip-flops, or shift register latches. For test purposes, the sequential elements in the multiple instantiated structures are loaded with test stimuli using known scan test techniques.
The invention defines at least one test mode wherein: a) sequential elements in each the repeated structures are organized for test into one or more scan chain segments such that the scan chain segments in each repeated structure are identical to corresponding segments in all other repeated structures, (i.e., the test connections within the repeated structures are identical in addition to the identical functional connections); b) each set of identical scan chain segments are clocked with identical or equivalent scan clocks such that all segments perform the same number of shifts at the same point in the test scan sequence; c) each of the identical scan chain segments are presented with scan data such that the same logic value is loaded into the first element of every such scan chain segment in each cycle of the test scan sequence, wherein: i) for any identical segments, a single scan data stream fans-out and is connected to the scan input of the first element of every such segment, the scan data stream being provided directly from a scan-in pin, from the output of a selected scan chain segment, or from a single output of a different set of such segments, and ii) where one of the scan chain segments follows another scan chain of segments, the individual outputs of the first segment are connected to one or more of the individual inputs of the second set; and finally d) every output of each scan chain segment is connected to the input of a subsequent scan chain segment or to a test observation point. The connection may be direct, or may involve a linear combination of the outputs of two or more non-identical scan chain segments. The test observation point may be a chip scan-out pin, or one of parallel inputs of a Multiple-Input Signature Register (MISR), wherein the overflow bit of the signature register is connected to a chip scan-out pin. Moreover, each replication of the repeated structure receives the same stimulus scan data. This is achieved by connecting the corresponding scan inputs of the repeated structure to the single scan data stream. Although, this change represents a significant departure from the Design For Test architecture of the chip, it has the distinct advantage of not requiring changes in the ATPG software.
In addition to organizing the scan chain segments and the fan-out of a single scan data stream to all identical parallel scan chain segments into multiple repeated structures, the invention further provides means for controlling the state of the storage elements requiring less test data in an amount approximately equal to the repetition count of the repeated structure. This forces testing corresponding faults in each copy of the repeated structure with a single test pattern, reducing the number of test patterns by a factor approximately equal to the repetition count of the replicated structure.